Professor Emmanuel Boutillon
University of South Britanny, France
| Organizer: IEEE Communications Society, Toronto Section |
| Title: Some Aspects of Hardware
Implementation of LDPC Codes |
| Speaker: Professor Emmanuel Boutillon University of South Britanny, France |
| Abstract: First, we propose an original VLSI architecture to reduce the hardware complexity of a Low-Density Parity Check (LDPC) decoder. The decoding algorithm is the Belief Propagation algorithm (BP) and both code and architecture are jointly constructed in a "decoder first code design" approach. The main characteristic of the architecture is a serial computation of the parity check using a quasi-optimal algorithm that reduces the memory requirements and algorithmic complexity by a factor of two compared to classical solutions. Second, we will present an application of almost 1 rate Medium Density Parity Check codes as a very efficient external code to suppress the flattening of high rate turbo codes. We will show that using the optimized architecture proposed, decoding complexity is very low. |
| Biography: Emmanuel Boutillon received the Engineering degree in telecommunications (1990) and his Ph.D. (1995), both from the Ecole Nationale Superieure des Telecommunications (ENST), Paris. From 1992 to 2000, he worked at ENST as an assistant professor, with a one year sabbatical stay at the University of Toronto in 1998. He is currently a professor at the University of South Britanny where he conducts research in the field of VLSI for digital telecommunications. |
| Time and Location: Thursday February 27, 2003, 11AM-12PM Refreshments at 6:00 p.m. Galbraith Building, Room 244 Faculty of Applied Science and Engineering University of Toronto, 35 St. George St. CONTACTS: IEEE Communications Society (Toronto Section): Co-Chair: Steve Hranilovic, M.A.Sc. E-mail: hranilovic@ieee.org Co-Chair: Andrew W. Eckford, M.A.Sc. E-mail: eckford@comm.utoronto.ca |
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