Seminar Announcement
These events are organized by various sub-sets of the IEEE Toronto Section.
The contact person listed below is the volunteer who has arranged this event.
Please use the e-mail link provided if you have any questions, suggestions,
or concerns.
| Title
|
Using advanced compiler technology to exploit the performance of the
Cell Broadband Engine architecture
(slides) |
| Speaker
|
Roch Archambault
Senior Technical Staff Member,
Compiler Optimization Technology and Compiler Focal Point for HPC
IBM Canada
8200 Warden Avenue,
Markham, Ontario L6G 1C7
Canada
|
| Day and Time
|
Thursday, October 26, 2006 6:30 p.m. to 8:00 p.m.
|
| Location
|
Ryerson University
Room ENG 106, George Vari Centre for Engineering and Computing
(located at the south east corner of Church and Gould Streets)
Toronto, Ontario map
|
| Organizers
|
IEEE Toronto Computer Chapter
|
| Contact
|
Visda
IEEE members and guests are welcome, no registration required.
|
| Abstract
|
The continuing importance of game applications and other numerically
intensive workloads has generated an upsurge in novel computer
architectures tailored for such functionality. Game applications feature
highly parallel code for functions such as game physics, which have high
computation and memory requirements, and scalar code for functions such
as game artificial intelligence, for which fast response times and a
full-featured programming environment are critical.
The Cell Broadband
Engine™ architecture targets such applications, providing both
flexibility and high performance by utilizing a 64-bit multithreaded
PowerPC® processor element (PPE) with two levels of globally coherent
cache and eight synergistic processor elements (SPEs), each consisting
of a processor designed for streaming workloads, a local memory, and a
globally coherent DMA (direct memory access) engine. Growth in processor
complexity is driving a parallel need for sophisticated compiler
technology. In this paper, we present a variety of compiler techniques
designed to exploit the performance potential of the SPEs and to enable
the multilevel heterogeneous parallelism found in the Cell Broadband
Engine architecture. Our goal in developing this compiler has been to
enhance programmability while continuing to provide high performance. We
review the Cell Broadband Engine architecture and present the results of
our compiler techniques, including SPE optimization, automatic code
generation, single source parallelization, and partitioning.
|
| Biography
|
Roch Archambault is a Senior Technical Staff Member at the IBM Toronto
Lab in the compiler development area. His most significant contributions
have been as an architect and technical lead in compiler back-end and
optimization technologies for IBM C, C++, and FORTRAN compiler products.
He has actively participated in High Performance Computing (HPC)
customer bid situations and played an important role supporting IBM HPC
marketing teams. Mr. Archambault has extensive experience in inventing
and producing code in the form of prototypes or fully implemented
features and is well known for his in-depth knowledge of compiler and
optimization technologies.
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