Seminar Announcement
These events are organized by various sub-sets of the IEEE Toronto Section.
The contact person listed below is the volunteer who has arranged this event.
Please use the e-mail link provided if you have any questions, suggestions,
or concerns.
| Title
|
Phase Locked Loop for Converter Synchronization and Synchronized
Sampling Application
|
| Speaker
|
Dr. Francis Dawson
University of Toronto
|
| Day and Time
|
Wednesday, February 7, 2007, 6:00 p.m. – 8:00 p.m.
6:00 Refreshments
6:30 Presentation
8:00 Conclusion
|
| Location
|
Room BA 1240
Bahen Centre
for Information Technology
University of Toronto - St. George Campus
40 St. George Street map - code BA |
| Organizer
|
Signals & Computational Intelligence Joint Chapter (AESS) |
| Contact
|
Ehsan Behboudi, E-mail:
|
| Abstract
|
A large number of converters utilized in industrial and utility applications must be synchronized to the grid. For power quality applications, the accuracy of spectral components calculated using the discrete Fourier transform is improved using synchronized sampling. Synchronization or synchronized sampling applications inherently require a phase locked loop. The conventional phase locked loop is constrained by
a trade-off between phase tracking performance and noise immunity. Moreover, most of the phase locked loops have a limited frequency tracking range which is not an issue in utility applications but is of great concern in some aerospace applications where the frequency of the bus can vary anywhere from 360 Hz to approximately 800 Hz in less than a second. This presentation gives a brief review of the state-of-the art for phase
locked loops followed by a brief description of a new phase locked loop concept
that has the following performance capabilities; 100:1 dynamic voltage range; positive sequence fundamental component tracking in real time; frequency tracking response time of at most two cycles; no tradeoff between noise immunity and tracking performance; maximum frequency tracking slewrate of 10 Hz/s, operating frequency range of subHz to 1 KHz. The new phase lock loop has been designed using a VHDL tool and can be
implemented in a field programmable gate array or with microprocessors. |
| Biography
|
Francis Dawson (S'86-M'87) received the B.Sc degree in physics and the B.ASc., M.A.Sc., and Ph.D degrees in electrical engineering from the University of Toronto in 1978, 1982, 1985, and 1988, respectively. He worked as a process control engineer in the pulp and paper, rubber and textile industries during the period 1978-1980. From 1982 to 1984 he acted as a consultant on various projects. Development areas included high- frequency link power supplies, power supplies for specialized applications and high current protection circuits. Since 1988 he has been with the Department of Electrical and Computer Engineering, University of Toronto where he is engaged in teaching and research. His areas of research interest include static power converters and their applications, signal processing in power engineering applications and device or process modeling. He has also participated as a Consultant or Project Leader in several industrial projects. Dr. Dawson is a member of the Association of Professional Engineers of Ontario. |
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