With four decades of continued scaling of conventional bulk and silicon-on-insulator (SOI) CMOS technologies, nonclassical MOSFET structures have been emerging, ranging from earlier (planar) partially-depleted (PD) or fully-depleted (FD) ultra-thin body (UTB) SOI MOSFETs, to emerging (vertical) common or independent symmetric/ asymmetric double-gate (s-DG/a-DG) or tri-gate (TG) FinFETs either on SOI or bulk-Si, and to recent surrounding-gate (SRG) silicon- nanowires (SiNW) such as omega-gate (?G) or gate-all-around (GAA) MOSFETs, all implementable with compatible CMOS technologies. Structural, process, and material parameters of these devices include gate workfunction, gate insulator thickness and dielectric constant, channel thickness and doping, in addition to device geometries such as channel length and width that, depending on device structure, are determined by lithography in planar devices or by process in vertical devices such as FinFET’s height and width or SiNW’s diameter.

In this talk, we present solution methods towards such a unified MOS compact model based on the unified regional modeling (URM) approach. Regional/explicit solutions are available for the generic doped a-DG in accumulation, depletion, weak/volume-inversion regions, and approximate solutions in inversion region for the two gate’s surface potentials. The unified solutions are obtained with smoothing functions, which contain the essential physics captured in the regional solutions that are otherwise impossible to obtain, and can be applied to terminal current/charge models with physical layer thickness and doping scalability. When the silicon body is undoped, without assuming either carrier type being at equilibrium, both carrier imrefs would be at non-equilibrium and, hence, bipolar conduction could result, which will be dependent on the contact type. The results demonstrate a first step towards unification of MOS compact models for the existing bulk/SOI and emerging MG MOSFETs with seamless transitions and selectable accuracy.

Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab supervisor of the computational nanoelectronics group. His current research focuses on development of compact models for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University, California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the recipient of the 2006 NSTI Fellow award.

Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits technical committees as well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region 10 (Australia, New Zealand & South Asia). He has served as an EDS distinguished lecturer since 2000. Since 2007 Dr. Zhou is an editor of the IEEE Electron Device Letters.