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Archive for the ‘Solid-State Circuits’ Category

SSCS Distinguished Lecture: Holistic Design in Optical Interconnects

Sunday, March 19th, 2017

Monday April 24, 2017 at 2:10 p.m. Dr. Azita Emami, Professor of Electrical Engineering and Medical Engineering at Caltech, will be presenting a distinguished lecture, “Holistic Design in Optical Interconnects”.

Day & Time: Monday, April 24th, 2017
2:10 p.m. – 3:30 p.m.

Speaker: Dr. Azita Emami
Professor of Electrical Engineering and Medical Engineering
Heritage Medical Research Institute Investigator
Deputy Chair of Division of Engineering and Applied Sciences
Caltech

Location: Room B024, Bahen Centre
40 St. George Street, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Organizers: IEEE Toronto SSCS

Cost: Free for everyone. Complimentary refreshments will be provided.

Abstract: The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.

Biography: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters

Friday, January 20th, 2017

Monday January 30, 2017 at 2:10 p.m. Professor Carlos Saavedra, Queen’s University and Associate Editor of the IEEE Transactions on Microwave Theory and Techniques, will be presenting “Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters”.

Event Slides: Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters

Speaker: Professor Carlos Saavedra
Queen’s University, Kingston
Associate Editor of the IEEE Transactions on Microwave Theory and Techniques

Day & Time: Monday, January 30th, 2017
2:10 pm – 3:00 pm

Location: Room WB116, Wallberg Building
184 College St, Toronto, ON M5S 3E4

Contact: Dustin Dunwell

Organizer: Solid State Circuit Society

Cost: Free for everyone.  Complimentary refreshments will be provided.

Abstract: Intermodulation distortion (IMD) refers to the phenomenon where the spectral lines of an information‐bearing signal interact with themselves to yield new, undesired, spectral lines as they pass through a circuit. While some of the spurious tones are easily eliminated through filtering, others are more difficult to deal with because they appear within the band of the information signal and interfere with it.  The study of IMD has a rich history and multiple techniques have been developed over time to mitigate it.  One such method is known as derivative superposition (DS), which reduces IMD distortion by using an auxiliary circuit to generate an out‐of‐phase replica of the IMD tones produced by the main circuit.  First introduced in the late 1990s, DS has attracted much attention due to its small footprint and low power consumption.  This talk will discuss work we have carried out at Queen’s that uses DS and digital assist to improve the output third‐order intercept point (OIP3) of gallium‐nitride (GaN) power amplifiers from by +40 dBm to +50 dBm over a 5 GHz span.  A stand‐alone distortion cancelling cell will also be presented which can improve the OIP3 of a generic off‐the‐shelf microwave amplifier by 7.5 dB. The talk will conclude with a discussion of mixer linearization using DS and digital assist techniques.

Biography: Carlos Saavedra obtained the Ph.D. degree from Cornell University, Ithaca, New York, in 1998. From 1998 to 2000 he was a Senior Engineer at Millitech Corporation (North Hampton, Massachusetts) and in 2000 he joined Queen’s University at Kingston where he currently holds the rank of Professor. He is an Associate Editor of the IEEE Transactions on Microwave Theory and Techniques, is a member of the Technical Program Review Committee of the IEEE International Microwave Symposium (IMS) and of the Steering Committee of the IEEE NEWCAS conference.  He is Past Chair of the IEEE MTT‐S Technical Coordinating Committee (TCC‐22) on Signal Generation and Frequency Conversion and was Guest Editor of the September 2013 IEEE Microwave Magazine Focus Issue titled “100 Years of Mixer Technology”. He served on the Steering and Technical Program Committees of the 2012 IEEE IMS and was a member of the IEEE RFIC Symposium TPC from 2008 to 2011.  Prof. Saavedra is a three‐time recipient of the third‐year ECE undergraduate teaching award at Queen’s University.  

Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies

Monday, September 19th, 2016

Wednesday November 23, 2016 at 2:10 p.m. Dr. Carlo Samori, Professor at Politecnico di Milano, Italy, will be presenting “Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies”.

Speaker: Dr. Carlo Samori
Professor, Politecnico di Milano, Italy

Day & Time: Wednesday, November 23, 2016
2:10 p.m. – 3:10 p.m.

Location: BA 1240
Bahen Centre for Information Technology
University of Toronto

Contact: Dustin Dunwell

Organizer: Solid State Circuit Society

Abstract: Despite having been the subject of extensive study in last 20 years for the solid-state IC community, the phase noise in voltage-controlled oscillators (VCOs) is still today an important research subject. The main reason is that phase noise is one of the main issues encountered during the design of a transceiver whose understanding is an essential know-how for an RF designer. A second reason is that the intrinsic time-variant nature of VCOs makes these circuits difficult to analyze, therefore new topologies are often proposed, claiming advantages in term of phase noise and/or dissipation that in several cases are hard both to understand and verify without a direct implementation.

This lecture will start from the basics of LC VCOs and of phase noise. The phase noise will be calculated in basic topologies and the fundamental trade-off with power dissipation and tuning range will be highlighted. The lecture then will continue by presenting advance VCO topologies, showing how these circuits typically aim to enhance either the current or the voltage efficiency, in order to improve the phase noise vs. power dissipation trade-off.

Biography: Carlo Samori received the Ph.D. in electrical engineering in 1995, at the Politecnico di Milano, Italy, where he is now a professor. His research interests are in the area of RF circuits, in particular of design and analysis of VCOs and high performance frequency synthesizers. He has collaborated with several semiconductor companies. He is a co-author of more than 100 papers and of the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). Prof. Samori has been a member of the Technical Program Committee of the IEEE International Solid-State Circuits Conference and he is a member of the European Solid-State Circuits Conference. He has been Guest Editor for the December 2014 issue of the Journal of Solid-State Circuits.

Time Varying Circuits for Radio Receiver Applications

Wednesday, May 18th, 2016

Thursday May 26th, 2016 at 2:10 p.m. Dr. Sudhakar Pamarti, Associate Professor at the University of California, will be presenting “Time Varying Circuits for Radio Receiver Applications”.

Speaker: Dr. Sudhakar Pamarti
Associate Professor, University of California, Los Angeles

Day & Time: Thursday, May 26th, 2016
2:10 p.m.

Location: Room BA 1210
Bahen Centre for Information Technology
University of Toronto, St. George Campus
40 St. George Street, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: Sharp, programmable, linear, integrated filters are enabling components for software defined and cognitive radio applications. However, they are difficult to realize: SAW and MEMS based filters are sharp and linear but not very programmable; active filters can be sharp and programmable but are not very linear; sampled charge domain filtering is sharp and programmable but the burden of the linearity is on the front end voltage-current converter. This talk descirbes an alternative approach that uses time-varying (as opposed to time-invariant) circuits to realize sharp, programmable, linear, integrated filters. The technique exploits sampling aliases to effectively realize very sharp, linear filtering prior to sampling. This talk will describe the basics of this time-varying circuit design approach and illustrates its application to radio front-ends and spectrum scanners. Measurement results from recent prototype integrated circuits will also be presented.

Biography: Dr. Sudhakar Pamarti is an associate professor of electrical engineering at the University of California, Los Angeles. He received the Bachelor of Technology degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur in 1995, and the M.S. and the Ph.D. degrees in electrical engineering from the University of California, San Diego in 1999 and 2003, respectively. Prior to joining UCLA, he has worked at Rambus Inc. (‘03-`05) and Hughes Software Systems (‘95-`97) developing high speed I/O circuits and embedded software and firmware for a wireless-in-local-loop communication system respectively. Dr. Pamarti is a recipient of the National Science Foundation’s CAREER award for developing digital signal conditioning techniques to improve analog, mixed-signal, and radio frequency integrated circuits. Dr. Pamarti serves as an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers.

Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables

Tuesday, February 23rd, 2016

Friday February 26th, 2016 at 11:10 a.m. Dr. Boris Murmann, Associate Professor at Stanford University, will be presenting “Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables”.

Speaker: Dr. Boris Murmann
Associate Professor, Electrical Engineering, Stanford University
IEEE Fellow, and Program Vice-Chair at ISSCC 2016

Day & Time: Friday, February 26th, 2016
11:10 a.m. – 12:40 p.m.

Location: BA1210, Bahen Centre for Information Technology, University of Toronto
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: The majority of textbook material on analog circuit design is based on the square-law model for MOS transistors. While this model remains useful for teaching, it has become too inaccurate for design in nanoscale CMOS. In circuit simulators, this problem has been solved using complex models equations with hundreds of parameters. Since these descriptions are impractical for manual use, designers tend to shy away from hand-analysis-based optimization and resort to a design style built on iterative and time-consuming “tweaking” in a simulator. This tutorial presents a systematic design methodology that bridges the gap between simulation, hand analysis and script-based optimization. The approach hinges upon Spice-generated look-up tables containing the transistor’s equivalent model parameters (gm, gds, etc.) across a multi-dimensional sweep of the terminal voltages. We interpret and organize these data based on the transistor’s inversion level, employing gm/ID as a proxy and key parameter for design. This width-independent metric captures a device’s efficiency in translating bias current to transconductance and spans nearly the same range in all modern CMOS processes (~3…30 S/A). When combined with other width-independent figures of merit (gm/Cgg, gm/gds, etc.) thinking in terms of gm/ID (rather than gate overdrive) allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. The final bias currents and device sizes follow from a straightforward denormalization step using the current density ID/W. Since this entire flow is driven by Spice-generated data, we maintain close agreement between the desired specs and the circuit’s simulated performance. We will detail the inner workings of this approach, and showcase its capabilities using a variety of practical examples.

Biography: Boris Murmann joined Stanford University in 2004, where he currently serves as an Associate Professor of Electrical Engineering. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Dr. Murmann’s research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium in 2008 and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits and as the Data Converter Subcommittee Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He currently serves as the program vice-chair for the ISSCC 2016. He is a Fellow of the IEEE.

Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects

Sunday, February 21st, 2016

Friday March 11th, 2016 at 4:10 p.m. Dr. Samuel Palermo, Associate Professor at Texas A&M University, will be presenting “Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects”.

Speaker: Dr. Samuel Palermo, Associate Professor
Associate Professor, Electrical and Computer Engineering Department, Texas A&M
IEEE Member and Associate Editor for IEEE Transactions on Circuits and Systems

Day & Time: Friday, March 11th, 2016
At 4:10 p.m., with social hour after the talk at Prenup Pub
Refreshments will be served at the pub

Location: BA1210, Bahen Centre for Information Technology, University of Toronto
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: The rapid growth of I/O bandwidth in applications such as datacenters and supercomputers motivate the development of interconnect architectures that can dramatically scale bandwidth density in an energy-efficient manner. This talk examines the potential of silicon photonic microring resonator-based optical transceivers for compact wavelength-division multiplexing (WDM) optical interconnects. An overview of the photonic devices typically found in a ring resonator optical interconnect platform is provided and the design of transceiver circuits which address key challenges related to the modulators and drop filters is described. The possibility of further improvements in bandwidth density via efficient implementations of >50Gb/s PAM4 modulation with the microring modulators is detailed.

Biography: Samuel Palermo received the B.S. and M.S. degree in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high-speed optical and electrical I/O architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently an associate professor. His research interests include high-speed electrical and optical interconnect architectures, high performance clocking circuits, and integrated sensor systems.

Dr. Palermo is a recipient of a 2013 NSF-CAREER award. He is a member of Eta Kappa Nu and IEEE. He currently serves as an associate editor for IEEE Transactions on Circuits and System – II and has served on the IEEE CASS Board of Governors from 2011 to 2012. He was a coauthor of the Jack Raper Award for Outstanding Technology-Directions Paper at the 2009 International Solid-State Circuits Conference and the Best Student Paper at the 2014 Midwest Symposium on Circuits and Systems. He received the Texas A&M University Department of Electrical and Computer Engineering Outstanding Professor Award in 2014 and the Engineering Faculty Fellow Award in 2015.

Linearization Techniques for Push-Pull Amplifiers

Sunday, January 10th, 2016

Thursday January 28, 2016 at 11:10 a.m. Dr. Rinaldo Castello, IEEE Fellow, will be presenting “Linearization Techniques for Push-Pull Amplifiers”.

Speaker: Dr. Rinaldo Castello
IEEE Fellow
University of Pavia, Italy

Day & Time: Thursday, January 28, 2016
11:10 a.m.

Location: University of Toronto, Bahen Centre, Room BA1230

Organizer: Solid-State Circuits Society

Contact: Dustin Dunwell

Abstract: Amplifiers that need to drive heavy loads (low resistances and/or large capacitances) or to handle high current signals with good efficiency generally use a push-pull output stage. This intrinsically creates large open-loop distortion components that need to be compressed through feedback to insure high closed-loop linearity. Minimizing close loop residual distortion involves three steps that will be discussed. First, eliminate all open-loop source of distortion not intrinsic to the proper operation of the push pull structure. Second, choose the amplifier topology that gives the maximum close loop compression of the open-loop distortion components for a given bandwidth. Third, maximize the open-loop gain in the signal band and/or the unity gain bandwidth of the amplifier for a given topology while insuring stability in the presence of variable loads.

Biography: Rinaldo Castello (S’78–M’78–SM’92–F’99) graduated from the University of Genova (summa cum laude) in 1977 and received the M.S. and the Ph. D. from the University of California, Berkeley, in ‘81 and ‘84. From ‘83 to ‘85 he was Visiting Assistant Professor at the University of California, Berkeley. In 1987 he joined the University of Pavia where he is now a Full Professor. He consulted for ST-Microelectronics, Milan, Italy up to 2005 in ‘98 he started a joint research centre between the University of Pavia and ST and was its Scientific Director up to ‘05. He promoted the establishing of several design centre from multinational IC companies in the Pavia area among them Marvell for which he has been consulting from 2005. Rinaldo Castello has been a member of the TPC of the European Solid State Circuit Conference (ESSCIRC) since 1987 and of the International Solid State Circuit Conference (ISSCC) from ‘92 to ‘04. He was Technical Chairman of ESSCIRC ’91 and General Chairman of ESSCIRC ‘02, Associate Editor for Europe of the IEEE J. of Solid-State Circ. from ’94 to ’96 and Guest Editor of the July ’92 special issue. From 2000 to 2007 he has been Distinguished Lecturer of the IEEE Solid State Circuit Society. Prof Castello was named one of the outstanding contributors for the first 50 and 60 years of ISSCC and a co-recipient of the Best Student Paper Award at the 2005 Symposium on VLSI of the Best Invited Paper Award at the 2011 CICC and of the Best Evening Panel Award at ISSCC 2012. He was one of the two European representatives at the Plenary Distinguished Panel of ISSCC 2013 and the Summer 2014 Issue of the IEEE Solid State Circuit Magazine was devoted to him. Rinaldo Castello is a Fellow of the IEEE.

SSCS Distinguished Lecture: Cognitive Radio Transceiver Chips

Monday, October 12th, 2015

Monday October 26, 2015 at 10:10 a.m. Eric Klumperink, Ph.D. and IEEE Respected Lecturer, will be presenting “Cognitive Radio Transceiver Chips”.

Powerpoint from the Presentation: 

Speaker: Eric Klumperink, Ph.D.

IEEE Respected Lecturer
Technical Proram Committee Member of ISSCC and RFIC
Associate Professor, Twente University, Enschede

Day & Time: Monday, October 26, 2015
10:10 a.m. – 11:10 a.m.

Location: Room RS 211, Rosebrugh Building, University of Toronto
164 College Street, Toronto, ON

Organizer: IEEE Toronto SSCS

Contact: Dustin Dunwell: dustin.dunwell@gmail.com

Refreshments will be served. All are welcome.

Abstract: A Cognitive Radio transceiver senses its radio environment and adaptively utilizes free parts of the radio spectrum. CMOS IC-technology is the mainstream technology to implement smart signal processing and for reasons of cost and size it is attractive to also integrate the radio frequency (RF) hardware in CMOS. This lecture discusses radio transceiver ICs designed for cognitive radio applications, with focus on analog RF. Cognitive radio asks for new functionality, e.g. spectrum sensing and more agility in the radio transmitter and flexibility in the receiver. Moreover, the technical requirements on the building blocks are more challenging than for traditional single standard applications, e.g. in bandwidth, programmability, sensing sensitivity, blocker tolerance, linearity and spurious emissions. Circuit ideas that address these challenges will be discussed, and examples of chips and their achieved performance will be given.

Biography: Eric Klumperink received his PhD from Twente University in Enschede, The Netherlands, in 1997. He is currently an Associate Professor at the same university where he teaches Analog and RF CMOS IC Design and guides research projects focussing on Cognitive Radio, Software Defined Radio and Beamforming. Eric served as Associate Editor for TCAS-I and II, and for the Journal of Solid-State Circuits. He is a technical program committee member of ISSCC and RFIC and is Respected Lecturer for IEEE. He holds several patents, authored and co-authored more than 150 international refereed journal and conference papers, and is a co-recipient of the ISSCC 2002 and the ISSCC 2009 “Van Vessem Outstanding Paper Award”.