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Archive for the ‘Solid-State Circuits’ Category

The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale

Thursday, November 29th, 2018

Monday December 17th, 2018 at 1:10 p.m. Dr. Sorin Voinigescu, Professor at the University of Toronto, will be presenting a SSCS distinguished lecture: “The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale”.

Day & Time: Monday December 17th, 2018
1:10 p.m. ‐ 2:30 p.m.

Speaker: Dr. Sorin Voinigescu
Professor, University of Toronto

Organizers: SSCS IEEE Toronto

Location: Bahen Centre, Room BA1230
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: Quantum computing is a hot topic at very cool temperatures. Cool as in 10-100 mK.

Recently, a cold-atom physicist nonchalantly asked me the question: Why are you interested in high temperature quantum computers? High as in 4 -12 K. He was serious! Need I talk about Global Warming in such cool environments? Pluto is another option. Today, quantum computers consist of racks of microwave and analog-mixed-signal test equipment, FPGAs and feedback loops for error correction, long 50-Ohm coaxial cables, and a few qubits formed with non-linear Josephson-junction resonators, entangled through niobium superconducting λ/4 resonators at 8-20 GHz, biased by a DC magnetic field of up to 1 Tesla, and whose spin is controlled by an AC magnetic field rotating in the “lab frame”. Are you still spinning?

There’s talk of electrons as “microwave photons”, Larmor and Rabi frequencies, photon-to-spin entanglement, RAP (as in rapid adiabatic passage), Bloch sphere, tensors in n-dimensional Hilbert spaces, but also of OFDM, phase noise, I-Q up- and down- conversion, Gaussian pulse modulation, coherent π/2, π/4 spin phase rotations in azimuth and elevation. Qubits are logic gates and memory cells at the same time. Logic gate operations consist of synchronized microwave pulses applied sequentially to the same qubits. The only probabilistic part (need I mention Schrodinger’s cats Flip and Flop?) is readout, when the spin state is projected on the Z (DC magnetic field) axis!

In other words, quantum computing is about everything you learned and thought you’d never use again, should have learned, or you were never taught in undergrad and grad school in math, quantum and atomic physics, electronics, electromagnetics, and computer science…

This talk will first attempt to demystify and translate the physics of quantum computing to an electronics engineer jargon. Next, I will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and explore their scalability through simulation to 2nm dimensions, when the coupling energy, ΔE, becomes comparable to thermal noise at 77-300 K.

Silicon electron-spin and hole-spin coupled quantum-dot (QD) qubits have attracted a lot of interest recently due to their potential for integration in commercial CMOS technology. However, like their more established superconducting cousins, to date, because of the low confinement and coupling energies (e.g. ΔE, in the tens of μeV range, comparable to the thermal noise level, kBT, at 100 mK) their operation has been restricted to temperatures below 100 mK. Moreover, since cryogenic systems cannot remove more than a few μW of thermal power at 100 mK, and the experimental laboratory (think TNC at U of T versus TSMC 7nm fab) technologies in which these qubits have been realized do not allow for fabrication of spin manipulation and readout circuitry, the latter reside on a separate chip, at 4 K or higher temperature. The lack of monolithic integration further degrades readout fidelity and computing speed because the atto-Farad capacitance, high-impedance qubit needs to drive 50Ω and 100x larger capacitance interconnect off- chip. A qubit with higher confinement and coupling energies, with spin resonance in the upper mm-wave region, will allow for higher temperature operation, alleviating these problems and enabling large-scale monolithic quantum computing processors. For example, a qubit operating at 4 K would require mode splitting energies of 0.25 meV which corresponds to a spin resonance frequency of 60 GHz and require a DC magnetic field of 2.5 T. Simplifying a bit, 240GHz spin-resonance frequencies and 9T magnetic fields should be adequate for 12K operation and 1.4 THz with an humongous magnetic field are needed for 77 K. You get the drift…
Finally, I will briefly review hot-off-the-press results obtained here at U of T. For the first time we report (i) integration of qubits and electronics on the same die, (ii) strained SiGe hole-spin and strained Si electron-spin FDSOI qubits on the same die, and (iii) propose a monolithic processor architecture which allows for short, 10-20ps spin control pulses and high Rabi frequencies, fRabi, to compensate for short spin phase coherence lifetime. We also demonstrate that, at 2 K, MOSFETs and cascodes can be operated as QDs in the subthreshold region while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively.

If we still have holiday time left, I will go through a tutorial example of how we can derive the specification for the mm-wave spin manipulation and readout circuits starting from the Hamiltonian and the measured I-V characteristics of our SiGe hole-spin qubits. I may touch on the impact of minimum-size (18nmx6nmx80nm) MOSFET ofset voltage and process variation on qubit characteristics, on spin manipulation and readout architectural options (low phase-noise radar, OFDM radio, low-noise, broadband, ultra-high-gain TIAs), mm-wave switch impact and OFDM sub-carrier spacing on qubit crosstalk and isolation…Or maybe we should leave that for New Years’.

SSCS Distinguished Lecture: Considerations and Implementations For High Data Rate Interconnect

Monday, November 5th, 2018

Thursday Nov 15, 2018 at 1:30 p.m. Dr. Daniel Friedman, Distinguished Research Staff Member, IBM T.J. Watson Research Center, will be presenting “SSCS Distinguished Lecture: Considerations and Implementations For High Data Rate Interconnect”.

Day & Time: Thursday November 15th, 2018
1:30 p.m. ‐ 2:30 p.m.

Speaker: Dr. Daniel Friedman
Distinguished Research Staff Member
IBM T.J. Watson Research Center

Organizers: IEEE Toronto Solid-State Circuits Society

Location: Bahen Centre Room B024
40 St. George Street
Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: Cloud computing requires many different interconnects. These links provide connectivity between and among CPUs, accelerators, memory, and switches; each link comes with its own distance and bandwidth requirements. Wireline transceivers are responsible for sending and receiving data from one chip to and from another, thus enabling required connectivity. Key specifications for such designs include data rate, power consumption, area, and connection distance. Distance and data rate specifications, in particular, drive the choice of physical channel to be used for the connection, which in turn drives requirements including the equalization capabilities of the transceiver. For short chip-to-chip channels with limited frequency-dependent loss, simple transceivers with little or no integrated equalization are appropriate, while for longer channels crossing backplanes and involving multiple transitions through connectors, complex transceivers with adaptive transmit and receive equalization are the right choice. As connection distances grow even longer, optical interconnect becomes an attractive option. In this talk, a framework for understanding serial link design will be presented, including a discussion of basic equalization strategies and key challenges. Next, several design examples will be presented, covering approaches to key classes of interconnect, from short reach channels to backplane channels to enabling highly integrated optical approaches. The talk will conclude with a discussion of emerging directions in this field.

Biography: Daniel Friedman is currently a Distinguished Research Staff Member and Senior Manager of the Communication Circuits and Systems department of the IBM Thomas J. Watson Research Center. He received his doctorate from Harvard University in 1992 and subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln labs, broadly in the area of image sensor design. After joining IBM in 1994, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include high-speed I/O design, PLL design, mmWave circuits and systems, and circuit/system approaches to enabling new computing paradigms. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the 2009 JSSC Best Paper Award (given in 2011), and the 2017 ISSCC Lewis Winner Outstanding Paper Award; he holds more than 50 patents and has authored or co-authored more than 75 publications. He was a member of the BCTM technical program committee from 2003-2008 and of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016. He has served as the Short Course Chair from ISSCC 2017 to the present and is a member of the SSCS Adcom since 2018.

Energy-Efficient Edge Computing for AI-driven Applications

Friday, August 17th, 2018

Thursday, November 22nd 2018, Vivienne Sze, Associate Professor at MIT in the Electrical Engineering and Computer Science Department, is presenting “Energy-Efficient Edge Computing for AI-driven Applications”.

Day & Time: Thursday November 22nd, 2018
4:10 p.m. ‐ 5:00 p.m.

Speaker: Vivienne Sze
Associate Professor, MIT in the Electrical Engineering and Computer Science Department

Organizers: IEEE Toronto Solid-State Circuits Society

Location: Sanford Fleming Building, Room 1105
10 King’s College Rd
Toronto, Ontario
Canada M5S 3G4

Contact: Dustin Dunwell

Abstract: Edge computing near the sensor is preferred over the cloud due to privacy and/or latency concerns for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics. However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning, computer vision, autonomous navigation and video/image processing. We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute, data movement and storage costs can be applied to various AI tasks including object detection, image classification, depth estimation, super-resolution, localization and mapping.

Biography: Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for portable multimedia applications, including computer vision, deep learning, autonomous navigation, and video process/coding. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee of ITU-T and ISO/IEC standards body during the development of High Efficiency Video Coding (HEVC), which received a Primetime Emmy Engineering Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014).

Prof. Sze received the B.A.Sc. degree from the University of Toronto in 2004, and the S.M. and Ph.D. degree from MIT in 2006 and 2010, respectively. In 2011, she received the Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT. She is a recipient of the 2018 Facebook Hardware & Software Systems Research Award, the 2017 Qualcomm Faculty Award, the 2016 Google Faculty Research Award, the 2016 AFOSR Young Investigator Research Program (YIP) Award, the 2016 3M Non-Tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2007 DAC/ISSCC Student Design Contest Award, and a co-recipient of the 2017 CICC Outstanding Invited Paper Award, the 2016 IEEE Micro Top Picks Award and the 2008 A-SSCC Outstanding Design Award.

For more information about research in the Energy-Efficient Multimedia Systems Group at MIT visit: http://www.rle.mit.edu/eems/

IEEE SSCS/CAS Distinguished Lecture Series – Dr. Gabor Temes

Thursday, July 26th, 2018

Friday, August 10th 2018, the IEEE Toronto SSCS/CAS invites you to the IEEE SSCS/CAS Distinguished Lecture Series on: “A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC” by Lukang Shi and Gabor C. Temes, and “Noise Filtering and Linearization of Single-Ended Circuits” by Gabor C. Temes et al., School of EECS, Oregon State University.

Date: Friday August 10th, 2018

Organizers: IEEE Toronto SSCS/CAS

Location: Bahen Centre Room BA1210

Lecture 1 (10:10am – 11:00am): A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC

Speakers: Lukang Shi and Gabor C. Temes
School of EECS, Oregon State University

Abstract: An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping. These topics will also be discussed.

Lecture 2 (11:10am – 12:00pm): Noise Filtering and Linearization of Single-Ended Circuits

Speakers: Gabor C. Temes et al.
School of EECS, Oregon State University

Abstract: The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for suppressing the effects of the low-frequency noise. In this paper, existing techniques are described for noise mitigation. Also, a novel approach is proposed, which can suppress low-frequency noise. In addition, the new process will also reduce even-order distortion, another major limitation of analog circuits. Finally, it may allow the use of single-ended circuits in applications where usually differential structures are needed.

Biography: Gabor C. Temes received the Ph.D. degree in electrical engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991. He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University.

Dr. Temes received the IEEE Leon K. Kirchmayer Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

Low Power Digital Equalization for High-Speed SerDes

Sunday, August 6th, 2017

Tuesday July 25, 2017 at 4:10 p.m. Dr. Masum Hossain, Assistant Professor at the University of Alberta, will be presenting “Low Power Digital Equalization for High-Speed SerDes”.

Day & Time: Tuesday July 25, 2017
4:10 p.m. – 5:10 p.m.

Speaker: Dr. Masum Hossain
Assistant Professor
University of Alberta

Location: Bahen Centre, room BA1180
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Organizers: Solid-State Circuits Society

Slides from Event: Low Power Digital Equalization for High-Speed SerDes

Abstract: High-speed signaling and Serdes architecture are evolving rapidly to accommodate higher data rates and higher insertion loss. Digital equalization is a natural progression to that tend where traditional analog equalization techniques are falling short to meet the performance demand of multilevel signalling. But digital equalization is also power consuming and mostly dominated by the analog to digital converters. This talk explores different power reduction techniques as well as higher information efficiency data converters to enable low power digital equalization at 10+ Gb/s in 65nm CMOS.

Biography: Masum Hossain received his Ph.D. at the University of Toronto in 2010. From 2008 to 2010 he worked for Gennum (now Semtech). From 2010 to 2013 he worked for Rambus. Since 2013 he joined faculty of engineering at University of Alberta. Masum won the best student paper award at the 2008 IEEE Custom Integrated Circuits (CICC) Conference. He also won Analog Device’s outstanding student designer award in 2010.

Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs

Friday, August 4th, 2017

Tuesday August 8, 2017 at 4:10 p.m. Dr. Shanthi Pavan, Professor of Electrical Engineering at the Indian Institute of Technology, will be presenting “Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs”.

Recording of the Event: https://drive.google.com/file/d/0B5wB8uI08dYvbmtnQjJoclF0VW8/view?usp=sharing

Day & Time: Tuesday August 8, 2017
4:10 p.m. – 5:10 p.m.

Speaker: Dr. Shanthi Pavan
Professor of Electrical Engineering
Indian Institute of Technology, Madras

Location: Bahen Centre, room BA1230
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Organizers: Solid-State Circuits Society

Abstract: Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various design alternatives for the design of power efficient single-loop continuous-time delta sigma converters.

Biography: Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engineering from the Indian Institute of Technology, Madras in 1995 and the Masters and Doctoral degrees from Columbia University, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras, where he is a Professor of Electrical Engineering. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr.Pavan is the recipient of many awards for teaching and research, including the IEEE Circuits and Systems Society Darlington Best Paper Award and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.

RF Integrated Harmonic Oscillators in Silicon Technologies

Thursday, May 4th, 2017

Friday June 9, 2017 at 2:10 p.m. IEEE Distinguished Lecturer and Professor at Lund University Pietro Andreani will be presenting “RF Integrated Harmonic Oscillators in Silicon Technologies”.

Event Media:
Event Slides
Recording of the Event

Day & Time: Friday June 9, 2017
2:10 p.m. – 3:30 p.m.

Speaker: Dr. Pietro Andreani
Professor, Lund University
IEEE Distinguished Lecturer and Professor

Location: University of Toronto
40 St. George Street
Toronto, Ontario Canada, M5S 2E4
Bahen Center of Information Technology
Room Number: B024

Free for everyone. Complimentary refreshments will be provided.

Contact: Dustin Dunwell

Organizers: Solid State Circuits Society

Abstract: As one of the truly fundamental analog functions in any wireless/wireline application, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation, we will investigate the mechanisms of phase noise generation in harmonic oscillators, including some recently published general results, after which we will analyze both classical and emergent oscillator architectures, describing pros and cons for each. Various techniques to achieve a very wide oscillator tuning range will be illustrated as well.

Biography: Pietro Adreani received the M.S.E.E. degree from the University of Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Sweden, in 1999. Between 2001 and 2007 he was chair professor at the Center for Physical Electronics, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund, Sweden. Since 2007, he has been associate professor at the department of Electrical and Information Technology (EIT), Lund University, working analog/mixed-mode/RF IC design. He is also the head of the VINNOVA Center for System Design on Silicon, hosted by EIT. He has been a TPC member of ISSCC (2007-2012), is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012, TPC chair in 2014) and RFIC, and Associate Editor of JSSC. He has been an IEEE SSCS Distinguished Lecturer since 2017. He has authored numerous papers on harmonic oscillators and phase noise.

SSCS Distinguished Lecture: Holistic Design in Optical Interconnects

Sunday, March 19th, 2017

Monday April 24, 2017 at 2:10 p.m. Dr. Azita Emami, Professor of Electrical Engineering and Medical Engineering at Caltech, will be presenting a distinguished lecture, “Holistic Design in Optical Interconnects”.

Day & Time: Monday, April 24th, 2017
2:10 p.m. – 3:30 p.m.

Speaker: Dr. Azita Emami
Professor of Electrical Engineering and Medical Engineering
Heritage Medical Research Institute Investigator
Deputy Chair of Division of Engineering and Applied Sciences
Caltech

Location: Room B024, Bahen Centre
40 St. George Street, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Organizers: IEEE Toronto SSCS

Cost: Free for everyone. Complimentary refreshments will be provided.

Abstract: The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.

Biography: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters

Friday, January 20th, 2017

Monday January 30, 2017 at 2:10 p.m. Professor Carlos Saavedra, Queen’s University and Associate Editor of the IEEE Transactions on Microwave Theory and Techniques, will be presenting “Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters”.

Event Slides: Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters

Speaker: Professor Carlos Saavedra
Queen’s University, Kingston
Associate Editor of the IEEE Transactions on Microwave Theory and Techniques

Day & Time: Monday, January 30th, 2017
2:10 pm – 3:00 pm

Location: Room WB116, Wallberg Building
184 College St, Toronto, ON M5S 3E4

Contact: Dustin Dunwell

Organizer: Solid State Circuit Society

Cost: Free for everyone.  Complimentary refreshments will be provided.

Abstract: Intermodulation distortion (IMD) refers to the phenomenon where the spectral lines of an information‐bearing signal interact with themselves to yield new, undesired, spectral lines as they pass through a circuit. While some of the spurious tones are easily eliminated through filtering, others are more difficult to deal with because they appear within the band of the information signal and interfere with it.  The study of IMD has a rich history and multiple techniques have been developed over time to mitigate it.  One such method is known as derivative superposition (DS), which reduces IMD distortion by using an auxiliary circuit to generate an out‐of‐phase replica of the IMD tones produced by the main circuit.  First introduced in the late 1990s, DS has attracted much attention due to its small footprint and low power consumption.  This talk will discuss work we have carried out at Queen’s that uses DS and digital assist to improve the output third‐order intercept point (OIP3) of gallium‐nitride (GaN) power amplifiers from by +40 dBm to +50 dBm over a 5 GHz span.  A stand‐alone distortion cancelling cell will also be presented which can improve the OIP3 of a generic off‐the‐shelf microwave amplifier by 7.5 dB. The talk will conclude with a discussion of mixer linearization using DS and digital assist techniques.

Biography: Carlos Saavedra obtained the Ph.D. degree from Cornell University, Ithaca, New York, in 1998. From 1998 to 2000 he was a Senior Engineer at Millitech Corporation (North Hampton, Massachusetts) and in 2000 he joined Queen’s University at Kingston where he currently holds the rank of Professor. He is an Associate Editor of the IEEE Transactions on Microwave Theory and Techniques, is a member of the Technical Program Review Committee of the IEEE International Microwave Symposium (IMS) and of the Steering Committee of the IEEE NEWCAS conference.  He is Past Chair of the IEEE MTT‐S Technical Coordinating Committee (TCC‐22) on Signal Generation and Frequency Conversion and was Guest Editor of the September 2013 IEEE Microwave Magazine Focus Issue titled “100 Years of Mixer Technology”. He served on the Steering and Technical Program Committees of the 2012 IEEE IMS and was a member of the IEEE RFIC Symposium TPC from 2008 to 2011.  Prof. Saavedra is a three‐time recipient of the third‐year ECE undergraduate teaching award at Queen’s University.  

Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies

Monday, September 19th, 2016

Wednesday November 23, 2016 at 2:10 p.m. Dr. Carlo Samori, Professor at Politecnico di Milano, Italy, will be presenting “Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies”.

Speaker: Dr. Carlo Samori
Professor, Politecnico di Milano, Italy

Day & Time: Wednesday, November 23, 2016
2:10 p.m. – 3:10 p.m.

Location: BA 1240
Bahen Centre for Information Technology
University of Toronto

Contact: Dustin Dunwell

Organizer: Solid State Circuit Society

Abstract: Despite having been the subject of extensive study in last 20 years for the solid-state IC community, the phase noise in voltage-controlled oscillators (VCOs) is still today an important research subject. The main reason is that phase noise is one of the main issues encountered during the design of a transceiver whose understanding is an essential know-how for an RF designer. A second reason is that the intrinsic time-variant nature of VCOs makes these circuits difficult to analyze, therefore new topologies are often proposed, claiming advantages in term of phase noise and/or dissipation that in several cases are hard both to understand and verify without a direct implementation.

This lecture will start from the basics of LC VCOs and of phase noise. The phase noise will be calculated in basic topologies and the fundamental trade-off with power dissipation and tuning range will be highlighted. The lecture then will continue by presenting advance VCO topologies, showing how these circuits typically aim to enhance either the current or the voltage efficiency, in order to improve the phase noise vs. power dissipation trade-off.

Biography: Carlo Samori received the Ph.D. in electrical engineering in 1995, at the Politecnico di Milano, Italy, where he is now a professor. His research interests are in the area of RF circuits, in particular of design and analysis of VCOs and high performance frequency synthesizers. He has collaborated with several semiconductor companies. He is a co-author of more than 100 papers and of the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). Prof. Samori has been a member of the Technical Program Committee of the IEEE International Solid-State Circuits Conference and he is a member of the European Solid-State Circuits Conference. He has been Guest Editor for the December 2014 issue of the Journal of Solid-State Circuits.