IEEE Toronto Section


Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables

Friday February 26th, 2016 at 11:10 a.m. Dr. Boris Murmann, Associate Professor at Stanford University, will be presenting “Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables”.

Speaker: Dr. Boris Murmann
Associate Professor, Electrical Engineering, Stanford University
IEEE Fellow, and Program Vice-Chair at ISSCC 2016

Day & Time: Friday, February 26th, 2016
11:10 a.m. – 12:40 p.m.

Location: BA1210, Bahen Centre for Information Technology, University of Toronto
40 St George St, Toronto, ON M5S 2E4

Contact: Dustin Dunwell

Abstract: The majority of textbook material on analog circuit design is based on the square-law model for MOS transistors. While this model remains useful for teaching, it has become too inaccurate for design in nanoscale CMOS. In circuit simulators, this problem has been solved using complex models equations with hundreds of parameters. Since these descriptions are impractical for manual use, designers tend to shy away from hand-analysis-based optimization and resort to a design style built on iterative and time-consuming “tweaking” in a simulator. This tutorial presents a systematic design methodology that bridges the gap between simulation, hand analysis and script-based optimization. The approach hinges upon Spice-generated look-up tables containing the transistor’s equivalent model parameters (gm, gds, etc.) across a multi-dimensional sweep of the terminal voltages. We interpret and organize these data based on the transistor’s inversion level, employing gm/ID as a proxy and key parameter for design. This width-independent metric captures a device’s efficiency in translating bias current to transconductance and spans nearly the same range in all modern CMOS processes (~3…30 S/A). When combined with other width-independent figures of merit (gm/Cgg, gm/gds, etc.) thinking in terms of gm/ID (rather than gate overdrive) allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. The final bias currents and device sizes follow from a straightforward denormalization step using the current density ID/W. Since this entire flow is driven by Spice-generated data, we maintain close agreement between the desired specs and the circuit’s simulated performance. We will detail the inner workings of this approach, and showcase its capabilities using a variety of practical examples.

Biography: Boris Murmann joined Stanford University in 2004, where he currently serves as an Associate Professor of Electrical Engineering. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Dr. Murmann’s research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium in 2008 and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits and as the Data Converter Subcommittee Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He currently serves as the program vice-chair for the ISSCC 2016. He is a Fellow of the IEEE.

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